The invention described herein relates to an interface for the transfer of data to and from a multi-bank dynamic random access memory (DRAM), and more particularly to an interface which provides for efficient utilization of bandwidth as well as minimum latency between receiving a request for transfer and the performance of such request.
As technology has evolved with regards to computer systems, there has been a demand for faster, high-capacity, random access memory (RAM) devices. RAM devices, such as dynamic random access memory (DRAM) are typically used as the main memory in computer systems. Conventionally, a DRAM is a memory that accesses data in a memory through use of timed asynchronous control signals. Although the operating speed of the DRAM has improved over the years, the speed has not reached that of processors used to access the DRAM. As such, slow access and cycle times of the DRAM may lead to system bottlenecks.
An improvement in memory speed has come in the form of a synchronous DRAM (SDRAM). A SDRAM is a clock driven memory that transfers data synchronously with the system clock. Specifically, input and output functions for the SDRAM are synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM. A typical SDRAM is configured to include multiple banks of memory cells for performing the read and write functions. Also included in the SDRAM are a number of row decoders employed so that word lines within each bank of memory cells can be controlled in an interleaved fashion to improve data transfer efficiency.
The inventor has recognized that in a DRAM device where multiple memory banks are employed, there are certain overhead functions initiated during read or write functions for the memory banks which may be hidden by performing concurrent operations for multiple memory banks. The inventor has further recognized that by controlling the configuration of data requests received from external sources, the bandwidth of data transferred may be increased and the latency with data requests that are entered may be reduced.
Described herein is a system and method for performing data transfers in a multi-array dynamic random access memory (DRAM) type device. Included in the system is a data buffer device which is connectable to the memory arrays. The data buffer device is configured such that it receives data requests from one or more devices in a computing system and provides for the data transfer according to the data request. In connection with the data buffer is a control circuit which provides for the selection of pending data requests and provides control signals to the data buffer to control the manner in which data requests are to be performed.
In particular, the control circuit is configured such that data transfers are performed with regards to the memory array in an interleaving fashion with regards to the plurality of memory banks. In one configuration of the invention, the memory array is configured to comprise a plurality of memory addresses where each address includes a bank 0 and bank 1. During operation of the memory device, data is transferred in an interleaving fashion between bank 0 and bank 1. The control circuit and the data buffer processes data requests in a manner such that the set-up functions performed with regards to transferring data for a particular bank may be performed while the actual data transfer is occurring for the other bank. For example, while a data transfer (i.e., read or write) is being performed for bank 0 at a particular address, a precharge function may be initiated for bank 1. Then, while the data transfer continues to bank 0, the activate function may be initiated for bank 1. Finally, when the data transfer for bank 0 is complete, the data transfer for bank 1 may be started.
The control circuit may be further configured such that data requests are performed in such a manner that each data request processed ends on a specified data boundary. For example, if each bank at a particular address is configured to receive eight words, such that each address is limited to a sixteen word data transfer, the control circuit may be configured such that regardless of the size of the data included in a particular data request, the request is only honored to the extent that bank 0 and bank 1 for a specified address are filled. This will be true even if the data request is for transferring an amount of data greater than that is available in a specified address. As such, the control circuit will not fulfill the whole request. In order to monitor amounts of data transferred, the system may include an apparatus which accounts for the amount of data transferred according to a particular request, and if the total amount is not transferred, generating a new data request which includes the untransferred data. In yet another configuration of the invention, the data request may be limited such that it does not exceed a particular size, for example sixteen words.
The control circuit may be further configured such that the interleaving process which provides one or more overhead operations may be performed when switching between different addresses in the memory array. As an example, the control circuit may initiate a precharge of bank 1 of an address for which a data transfer has been performed, while performing an activate of bank 0 in an address to which a future data transfer is to be performed. This type of overlapping function may further be performed while the system is switching between data requests from different devices in the disk drive.
In operation, the system described herein detects one or more requests for a data transfer from other devices within the disk drive. Upon selection of a particular data request to honor, an address in the memory to make the transfer is identified. As was discussed above, the particular address will include a bank 0 and a bank 1 and a determination will be made wherein either bank 0 or bank 1 the data transfer is to begin.
At this point, the system will begin performing all the overhead functions necessary for performing the data transfer. These include the activation of the bank, the actual performance of the data transfer, as well as the precharge and equalization of the memory cells. As was described above, the steps are performed in such a manner that steps for bank 0 and bank 1 are performed concurrently. During the actual data transfer, a monitoring process is performed whereby only enough data is read from or written to a particular address. Once the data transfer for that particular address is complete, a xe2x80x9cdonexe2x80x9d command is transmitted to the device which had made the data request.
During the performance of the transfer, the data device monitors the amount of data transferred and upon receiving the xe2x80x9cdonexe2x80x9d command, makes a determination as to whether all data identified in the data request has been transferred. The monitoring process may be performed through a count of the data strobe signal to determine how many words were transferred. If a determination is made that not all the requested data has been transferred, the data device will reconstitute its data request and provide it to the data buffer.